Circuit device for realizing a non-linear reactive elements scale network

ABSTRACT

The invention relates to a circuit device for realizing a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive and capacitive components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component of the network is formed by cascade connecting a first and a second transconductance integrator with each other.

FIELD OF THE INVENTION

[0001] The present invention relates to a circuit device for realizing anon-linear reactive elements scale network.

BACKGROUND OF THE INVENTION

[0002] As it is well known in this technical field, for applicationsrelating to non-linear decoding channels for digital transmission,electronic devices capable of implementing a scale network comprising LCnon-linear elements would be needed. In fact, research carried out bythe Applicant indicates that a non-linear channel would provide improvedperformance with respect to a standard transmission channel.

[0003] For example, the here-attached FIG. 1 schematically illustratesthe structure of a scale network comprising n LC non-linear elementscascade connected together.

[0004] The network of FIG. 1 is essentially a quadrupole having a pairof input terminals to which a voltage potential Vo is applied, andhaving a pair of output terminals to which a resistive load Rt isconnected.

[0005] All the pairs of LC non-linear elements, which is L1, C1; . . . ,Li, Ci, . . . , Ln, Cn, have the same value. In other words, all the Lcomponents are identical with one another, as are the C components.

[0006] In particular, the non-linear equations that the network of FIG.1 would be expected to implement are the following: $\begin{matrix}{{{Equation}\quad (1)}{C = \frac{C_{0}}{1 + ( \frac{V_{C}}{V_{0}} )^{2}}}} & (1)\end{matrix}$

[0007] where, C₀ and V₀ are constants; and $\begin{matrix}{{{Equation}\quad (2)}{L = \frac{L_{0}}{1 + ( \frac{I_{L}}{I_{0}} )^{2}}}} & (2)\end{matrix}$

[0008] where, L₀ and I₀ are constants.

[0009]FIG. 2 shows schematically a possible circuit embodiment based onthe use of a derivator.

[0010] A bipolar transistor differential cell BJT receives a biascurrent I1 on a first circuit branch, and it is connected to ground by acurrent generator I. A potential equal to Vc lies across the emitterterminals of the transistor pair.

[0011] A transistor output stage, being supplied by a current Ic, isconnected to said first circuit branch and has an output terminalconnected to ground through the parallel of a capacitance and a currentgenerator.

[0012] This embodiment is based on the following approximate equation:$\begin{matrix}{{{Equation}\quad {(3)\lbrack {1 + ( \frac{V_{C}}{V_{0}} )^{2}} \rbrack}^{- 1}} \cong {{hyp}\quad \sec \quad {h^{2}( \frac{V_{C}}{V_{0}} )}}} & (3)\end{matrix}$

[0013] The exponential voltage-current characteristic of the transistorpair BJT of the differential cell allows the desired non-linearequations to be synthesized where the substitution indicated in Equation(3) is carried into effect.

[0014] However, the dynamic performance of this hypothetical embodimentbased on the use of a derivator would be inadequate to meet therequirements of the above application field.

[0015] If taking into consideration the non-linear capacitance alone, apossible embodiment of the network of FIG. 1 could be provided throughthe use of an integrator instead of a derivator. In this way, thesuperior dynamic characteristics of the integrator with respect to thederivator could be exploited.

[0016] An embodiment based on an integrator should implement thefollowing operations: $\begin{matrix}{{{Equation}\quad (4)}{I_{C} = { {\frac{C_{0}}{1 + ( \frac{V_{C}}{V_{0}} )^{2}}\frac{\partial V_{C}}{\partial t}}\Rightarrow{\frac{1}{C_{0}}{\int{{I_{C}\lbrack {1 + ( \frac{V_{C}}{V_{0}} )^{2}} \rbrack}{t}}}}  = V_{C}}}} & (4)\end{matrix}$

[0017] from which it is evinced that two multipliers would be needed.

[0018] A circuit device realized according to Equation (3) would behighly complicated. Moreover this would be even worse since the scalenetwork of FIG. 1 contains n LC pairs and, when the number n is greaterthan 10, as required in most applications, the complexity of the circuitembodiment would limit high-frequency performance.

SUMMARY OF THE INVENTION

[0019] The underlying technical approach to this invention is to providea circuit device for realizing a non-linear reactive elements network,which device has suitable structural and functional features for thenetwork to be implemented by minimizing complexity occupied area, andthis without employing integrated inductors.

[0020] The principles of the present invention are based on implementingthe scale network by using transconductance integrators that simulatenon-linear inductors.

[0021] On the basis of the above idea, the technical problem is solvedby a device as previously indicated and as defined in the characterizingpart of claim 1 herewith enclosed.

[0022] More particularly, in one embodiment the invention relates to acircuit device for realizing non-linear reactive elements scale network,wherein the non-linear elements in the network are pairs of inductiveand capacitive components cascade connected between a pair of inputterminals and a pair of output terminals.

[0023] The invention applies specifically to read-channel devices forhard disk drivers (HDDs), and broadly to digital communication systems,being part of a substitutive architecture of the so-called“partial-maximum likelihood response” (PRML) systems. This because it isconsidered that a “non-linear channel”, based on the scale network asabove, can provide stronger information decoding as for noise ifcompared to a standard scale (e.g., PRML, Peak Detection, etc.).

[0024] The features and advantages of the device according to theinvention will become apparent from the following description of anembodiment thereof, given by way of non-limitative example withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 shows schematically a scale network comprising n LCnon-linear elements.

[0026]FIG. 2 shows schematically a conventional circuit based on a 20derivator for implementing the scale network of FIG. 1.

[0027]FIG. 3 shows schematically a circuit device according to thisinvention.

[0028]FIG. 4 is schematical view of the circuit detail of the device inFIG. 3.

[0029]FIG. 5 shows schematically a portion of the scale networkaccording to this invention realized by means of several devices of FIG.3.

DETAILED DESCRIPTION

[0030] With reference to the drawings, in particular to the embodimentsillustrated by FIGS. 3, 4, and 5 schematically shown is a circuitaccording to the invention for implementing a network 5 of reactive LCnon-linear elements, e.g., a network as shown schematically in FIG. 1.

[0031] The device 1 has a pair of input terminals A, B on whichdifferential input voltages Vin+ and Vin−, are respectively applied.

[0032] The device 1 also has a pair of output terminals O1, O2 wheredifferential output voltages Vout+ and Vout− are respectively produced.

[0033] The input terminals A, B are parts of a first transconductance(Gm1) integrator 2.

[0034] The differential output pair U1, U2 of this first integrator Gm1are connected each to a respective differential input A2, B2 of a secondtransconductance (Gm2) integrator 3. These outputs O1 and O2 are coupledto a feedback CMFB (Common Mode FeedBack) block 4 arranged to provide areference signal CMFB_ref for the bias circuit portion of the secondintegrator 3.

[0035] In a preferred embodiment, the transconductance Gm1 of the firstintegrator 2 has the same value as the transconductance Gm2 of thesecond integrator 3. The outputs U1, U2 are also coupled to groundthrough respective diodes Q5 and Q6, having their high impedance inputcoupled to the output lines. The second integrator 3 has differentialoutputs that are coincident with the outputs O1 and O2 of the device 1.

[0036] The outputs O1, O2 of the device 1 are further coupled to groundthrough respective stabilization capacitors C₀, C₁.

[0037] Briefly, the differential input voltage Vin+, Vin− corresponds tocurrent Ic of Equation (4), and the differential output voltage Vout+,Vout− corresponds to voltage Vc of the same Equation (4).

[0038] The integrator pair 2 and 3 basically simulate the frequencyperformance of a capacitance C in the scale network of FIG. 1.

[0039] Also the non-linear inductor L may be implemented through anidentical integrator pair design.

[0040] When implementing the inductor, L, the differential input voltageVin+, Vin− corresponds to voltage V of the inductor, and thedifferential output voltage Vout+, Vout− corresponds to current I_(L).

[0041] The device 1 of this invention has, therefore, no integratedinductors, so that the circuit complexity and overall occupied area ofthe device can be minimized.

[0042]FIG. 4 schematically shows in greater circuit detail the structureof device 1.

[0043] In one embodiment, both the first and the second integrators 2and 3, respectively are formed with mixed bipolar-MOS technology bymeans of bipolar transistor differential cells biased by MOS circuitportions. Other circuit designs may be used.

[0044] The first integrator 2 comprises a differential cell having adouble pair of transistors, Q1, Q2 and Q3, Q4, which is associated withthe differential inputs A, and B.

[0045] A bias circuit portion, comprising MOS transistors M1, . . . ,M6, is arranged to couple the differential cell with the supply voltagereferences Vdd and the bias voltage and current references I1 and V1.

[0046] The transistors Q5, Q6 and Q7, diode configured, couple theoutputs U1, U2 of the first integrator 2 to ground.

[0047] The outputs U1, U2 of the integrator 2 are connected to therespective inputs A2, B2 of the second integrator 3, the latter showinga differential cell structure of bipolar transistors with a double pairof input transistors Q8, Q9 and Q10, Q11.

[0048] A bias circuit portion comprised of MOS transistors M7, M8, M9and M10 couples the differential cell of integrator 3.

[0049] A feedback block 4 connects the outputs O1, O2 of the secondintegrator 3 to the bias circuit portion in order to provide a voltagereference CMFB_ref for the transistor pair M7, M9.

[0050] A capacitance with value Co/2 is inserted across the outputs O1and O2.

[0051] As said before, the device 1 allows the performance of one of thenon-linear components of the scale network of FIG. 1, both thecapacitive component C and the inductive component L, to be emulated.

[0052] Thus, the scale network structure can be reconstructed by using aplurality of suitably interconnected devices 1.

[0053] Shown in FIG. 5 is an exemplary portion of a scale networkrealized by connecting several devices 1 together, which are similar tothe device described hereinabove.

[0054]FIG. 5 shows a first device 1, emulating a first inductor L1, asbeing connected to the voltage generator Vo at the first differentialinput A.

[0055] The output O1 is connected to ground, and the output O2 isconnected to the differential input A of a second device 1 emulating thecapacitor C1.

[0056] The output O2 of the second device emulating C1, is connected tothe differential input B of the first device emulating L1.

[0057] The output O1 of the second emulating C1, is connected to thedifferential input A of a third device 1 emulating a second inductor L2in the scale network.

[0058] The output O1 of the third device emulating L2 is connected tothe differential input B of the second device emulating C1, and so on.

[0059] In this way, a non-linear scale network can be implemented withat least twenty LC elements, without using integrated inductors.

[0060] The network implemented with a cascade of devices 1 according tothe invention has shown to have excellent characteristics of frequencyresponse.

[0061] In addition, the total circuit area occupied by the cascade ofdevices 1 is smaller than that required by conventional designs.

[0062] Lastly, the non-linear scale network of the invention allows acascade connection of many more elements than in conventional designs.

[0063] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A circuit for realizing a non-linear reactive elements scale network,comprising: a plurality of non-linear elements of the network acting asinductive and capacitive components cascade connected between a pair ofinput terminals and a pair of output terminals, characterized in thateach component of the network being formed by cascade connecting a firstand a second transconductance integrator with each other.
 2. The circuitaccording to claim 1 wherein each integrator comprises a bipolartransistor input circuit portion and a MOS transistor bias circuitportion, and that the outputs of the second integrator are feedbackconnected to the bias circuit portion of the same integrator through afeedback block.
 3. The circuit according to claim 2 wherein saidfeedback block provides a voltage reference for said bias circuitportion.
 4. The circuit according to claim 1 wherein the outputs of thefirst integrator connected to the inputs of the second integrator arefurther coupled to ground by respective diodes.
 5. The circuit accordingto claim 1 wherein it comprises differential outputs respectivelycoupled to ground through a stabilization capacitance.
 6. The circuitaccording to claim 1 wherein the first and the second integrator havethe same transconductance.
 7. The circuit according to claim 1 whereineach pair of integrators implements the following equation, in order toemulate a capacitor, or a similar equation with L indexes in order toemulate an inductor: $\begin{matrix}{I_{C} = { {\frac{C_{0}}{1 + ( \frac{V_{C}}{V_{0}} )^{2}}\frac{\partial V_{C}}{\partial t}}\Rightarrow{\frac{1}{C_{0}}{\int{{I_{C}\lbrack {1 + ( \frac{V_{C}}{V_{0}} )^{2}} \rbrack}{t}}}}  = V_{C}}} & (4)\end{matrix}$


8. The circuit according to claim 1, wherein the plurality comprises atleast twenty inductive and capacitive components.
 9. A circuit,comprising: a circuit input; a plurality of non-linear inductorsimulation components, each having an input and an output, the input ofthe non-linear inductor simulation components being coupled to thecircuit input; a plurality of non-linear capacitor simulationcomponents, each having an input and an output; a coupling from anoutput of at least one of the non-linear inductor simulation componentsto the input of at least one of the non-linear capacitor simulationcomponents; a coupling from an output of at least one of the non-linearcapacitor simulation components to the input of at least one of thenon-linear inductor simulation components; and a circuit output coupledto the output of the non-linear capacitor simulation components.
 10. Thecircuit according to claim 9, further including: a common mode feedbackcircuit coupled to the circuit output.
 11. The circuit according toclaim 9, further including: a feedback circuit coupled to the circuitoutput in order to provide a reference signal level for the feedback.12. The circuit according to claim 9 wherein the circuit input is adifferential input.
 13. The circuit according to claim 9 wherein theinductor simulation circuit includes bipolar transistors.
 14. Thecircuit according to claim 9 wherein the inductor simulation circuitincludes MOS transistors.
 15. The circuit according to claim 9, furtherincluding: a disk drive read channel signal line coupled to the circuitinput to provide data stored on a disk drive to the circuit.
 16. Amethod of simulating a capacitive and inductor network comprising:receiving a differential input signal at a simulated non-linear inductorcircuit; integrating the input signal to simulate a non-linear inductorand outputting the results; receiving a differential input signal fromthe output of the non-linear inductor at a simulated non-linearcapacitor circuit; integrating the differential input signal to simulatea non-linear capacitor; and outputting the integrated capacitor signalas the output of the circuit.
 17. The method according to claim 16,further including: feeding back an output from the capacitor circuit toat least one input of the inductor simulation circuit.
 18. The methodaccording to claim 16, further including: receiving the input signalfrom a Disk drive read channel.